1. Field of the Invention
The present invention relates to a method and system for compensation of frequency pulling in an all digital phase lock loop.
2. Description of Related Art
A conventional phase lock loop generates an output having an output frequency. The output frequency generally includes a desired oscillation frequency. To generate the output, the conventional phase lock loop utilizes a multi-phase oscillator which includes a plurality of latches. However, such latches have impedance values, such as variable capacitance values that periodically fluctuate depending on the polarity of a reference clock signal that is used to clock the latches. This fluctuation in the variable capacitance value causes frequency pulling in the multi-phase oscillator and generates, for example, spurs in the output frequency. Such spurs can be periodic in the output frequency, and one or more spurs can be located at a frequency close to the desired oscillation frequency.
Generally spurs are undesirable since they reduce the likelihood that the output of the conventional phase lock loop will conform to specifications such as the 3rd Generation Partnership Project (“3GPP”) specifications. The number of spurs and/or the closeness in frequency to the desired oscillation frequency may decrease performance significantly.
Thus, there is a need for a method and system for compensation of frequency pulling in an all digital phase lock loop.